Certain processing schemes and architecture are disclosed in Patent Cooperation Treaty Application No. PCT/US2008/002058, entitled, SOLAR CELL WITH TEXTURED SURFACES, filed Feb. 15, 2008, in the names of Emanuel M. Sachs and James F. Bredt and The Massachusetts Institute of Technology, designating the United States of America, and also claiming priority to two provisional United States applications, No. U.S. 60/901,511, filed Feb. 15, 2007, and No. U.S. 61/011,933, filed Jan. 23, 2007. All of the PCT application and the two US provisional applications are hereby incorporated fully herein by reference. The technology disclosed in these applications is referred to herein collectively as Self Aligned Cell (SAC) technology.
Provisional U.S. Patent application Ser. No. 61/201,595, entitled WEDGE IMPRINT PATTERNING OF IRREGULAR SURFACE, filed on Dec. 12, 2008, relates to matters disclosed herein and priority is hereby claimed to and the benefit of this provisional application 61/201,595 is hereby claimed and it is hereby fully incorporated herein by reference.
Provisional U.S. Patent application Ser. No. 61/124,608, entitled PRINTING ASPECTS OF SELF ALIGNED CELL ARCHITECTURE, filed on Apr. 18, 2008, relates to matters disclosed herein and priority is hereby claimed to and the benefit of this provisional application 61/124,608 is hereby claimed and it is hereby fully incorporated herein by reference.
It is desirable to have efficient methods for patterning of silicon wafers with point and line features to define regions to be etched, allowing the formation of light-trapping texture and other topographic features for use in photovoltaic (PV) cells. Modern silicon solar cells are on the order of 200 μm thick, so it is desirable that the size of the etched features be on the order of 20 μm or smaller, to limit the quantity of valuable silicon lost to etching and associated mechanical weakness of the wafer. Economical sawn silicon wafer stock has significant surface roughness, so it is further desirable that the patterning methods be compatible with rough surfaces.
The highest efficiency laboratory PV cells make routine use of patterning by photolithography to precisely define texture and metallization regions, but these methods are generally not used in industrial production of cells due to cost and rate issues. Limited manufacturing use of photolithography may be feasible in some cases but even in best case scenarios costs will be high, primarily due to the specialized nature of the photochemicals required, the many process steps involved, and the associated yield losses. Subsidiary challenges include reducing the extreme waste of resist material inherent in film forming by spin coating, focusing an exposure on multicrystalline substrates with variable thickness, and the high capital cost of projection lithography equipment.
Non-photolithographic patterning methods that are known include soft lithographic techniques and nanoimprint lithography. Soft lithography involves use of an elastomeric stamp with raised planar (flat-topped) features to define a pattern at the micro or nanoscale. The earliest soft lithographic techniques involve deposition of fragile self-assembled monolayers which are limited in their ability to withstand strong etch chemistries. Subsequent soft lithographic techniques involve thermal or photocuring of specialized polymers within channels in a stamp, which limits the general applicability of the technique and has similar materials cost issues as photolithography. Soft lithographic techniques are not presently in industrial use at manufacturing scale.
Nanoimprint lithography is another non-photolithographic patterning technique that involves deformation of a polymeric film by means of a tool with raised planar features that are stiff relative to the polymeric film. It is targeted at ultrafine features of ˜20 nm size for VLSI applications, where optical diffraction effects render photolithography problematic. The use of hard tools limits the technique to conventional polished substrates, and generally a thin residue layer is present on the surface of the substrate in the imprinted regions following imprint, which must be removed by dry etching under vacuum in a subsequent step. One electronics manufacturing company has qualified nanoimprint lithography for use in making high performance nanometer-scale microchips, but cost and rate limitations likely preclude its use on large, lower value substrates such as solar cells. Also, the forces involved (on the order of 1900 psi) would likely crack fragile irregular multicrystalline silicon wafers. Nanoimprint lithography does not appear to be in widespread industrial use and has not seen significant development in other industries.
A variety of printing techniques are known for producing patterns of polymer inks, including screen printing, gravure printing, offset printing, and flexographic printing, and these techniques are amply fast for solar cell processing, but these techniques are generally limited to feature sizes on the order of 75-100 μm or larger, too large for patterning texture. Dynamic squeeze-out of ink during printing, also known as “dot gain” limits the quality of these processes at the lower limit of size.
The known techniques described above have limitations that render them inappropriate for industrial patterning of surface texture on standard silicon solar cells. It is therefore desirable to have a low-cost process capable of micron-scale patterning of the irregular surfaces of the multicrystalline wafer stock that is typical in the PV industry. It is further desirable that such a method make efficient use of inexpensive resist materials, that it require relatively few processing steps, and that it be suitable for high speed continuous processing at rates on the order of one wafer per second.